View LSM303DLH_4888211.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LSM303DLH
Sensor module: 3-axis accelerometer and 3-axis magnetometer
Features

Analog supply voltage: 2.5 V to 3.3 V Digital supply voltage IOs: 1.8 V Power-down mode 3 magnetic field channels and 3 acceleration channels 1.3 to 8,1 gauss magnetic field full-scale 2 g/4 g/8 g dynamically selectable fullscale 16-bit data out I2C serial interface 2 independent programmable interrupt generators for free-fall and motion detection Embedded self-test Accelerometer sleep-to-wakeup function 6D orientation detection ECOPACK(R) RoHS and "Green" compliant (see Section 10) and a 3D digital magnetic sensor. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are realized using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM303DLH has a linear acceleration full-scale of 2 g / 4 g / 8 g and a magnetic field full-scale of 1.3 / 1.9 / 2.5 / 4.0 / 4.7 / 5,6 / 8.1 gauss, both fully selectable by the user. The LSM303DLH includes an I2C serial bus interface that supports standard mode (100 kHz) and fast mode (400 kHz). The internal self-test capability allows the user to check the functioning of the whole module in the final application. The system can be configured to generate an interrupt signal by inertial wakeup/free-fall events, as well as by the position of the device itself. Thresholds and timing of interrupt generators are programmable on the fly by the end user. Magnetic and accelerometer parts can be enabled or put in power-down mode separately. The LSM303DLH is available in a plastic land grid array (LGA) package, and is guaranteed to operate over an extended temperature range from -30 to +85 C. Table 1. Device summary
Temp. range [C] Package Packing Tray -30 to +85 LSM303DLHTR LGA-28 Tape and reel
LGA-28L (5x5x1.0 mm)
Applications

Compensated compassing Map rotation Position detection Motion-activated functions Free-fall detection Intelligent power-saving for handheld devices Display orientation Gaming and virtual reality input devices Impact recognition and logging Vibration monitoring and compensation
Part number LSM303DLH
Description
The LSM303DLH is a system-in-package featuring a 3D digital linear acceleration sensor
December 2009
Doc ID 16941 Rev 1
1/47
www.st.com 47
Contents
LSM303DLH
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 2.2 2.3 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 2.3.2 Accelerometer sensor I2C - inter IC control interface . . . . . . . . . . . . . . 14 Magnetic field sensing I2C digital interface . . . . . . . . . . . . . . . . . . . . . . 15
3 4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 4.3 Linear acceleration sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sleep-to-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 5.2 5.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Linear acceleration self-test operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Magnetic self-test operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 6.2 6.3 6.4 6.5 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Digital interface power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 High current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/47
Doc ID 16941 Rev 1
LSM303DLH 7.1.2 7.1.3
Contents Linear acceleration digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Magnetic field digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 9
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1 Linear acceleration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.1.10 9.1.11 9.1.12 9.1.13 9.1.14 9.1.15 9.1.16 9.1.17 9.1.18 9.1.19 CTRL_REG1_A (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG2_A (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG3_A (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG4_A (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG5_A (24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ) 33 HP_FILTER_RESET_A (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 REFERENCE_A (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STATUS_REG_A(27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OUT_X_L_A (28h), OUT_X_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 34 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . 34 OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . 34 INT1_CFG_A (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_SRC_A (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_THS_A (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_DURATION_A (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT2_CFG_A (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT2_SRC_A (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT2_THS_A (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT2_DURATION_A (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2
Magnetic field sensing register description . . . . . . . . . . . . . . . . . . . . . . . 39
9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 CRA_REG_M (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CRB_REG_M (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MR_REG_M (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 OUT_X_M (03-04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 OUT_Y_M (05-06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 OUT_Z_M (07-08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SR_REG_M (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 IR_REG_M (0Ah/0Bh/0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Doc ID 16941 Rev 1
3/47
Contents
LSM303DLH
10 11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4/47
Doc ID 16941 Rev 1
LSM303DLH
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Magnetic ST (positive bias) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Operational mode and power supply for magnetic field sensing . . . . . . . . . . . . . . . . . . . . 21 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 24 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 25 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CTRL_REG1_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG1_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 29 Normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 30 CTRL_REG2_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG2_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 High-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG3_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG3_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Data signal on INT 1 and INT 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG4_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG4_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG5_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CTRL_REG5_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Sleep-to-wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 REFERENCE_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 REFERENCE_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STATUS_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STATUS_REG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 INT1_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT2_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT2_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT2_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 16941 Rev 1
5/47
List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 74. Table 75. Table 76. Table 77.
LSM303DLH
Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT2_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT2_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT2_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT2_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CRA_REG_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CRA_REG_M description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CRA_REG M description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CRA_REG_M description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CRA_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CRA_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MR_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 MR_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Magnetic sensor operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 OUTXH_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 OUTXL_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 OUT_YH_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 OUT_YL_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 OUTZH_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 OUTZL_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 IRA_REG_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 IRB_REG_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 IRC_REG_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6/47
Doc ID 16941 Rev 1
LSM303DLH
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LSM303DLH electrical connection 1 - recommended for I2C fast mode . . . . . . . . . . . . . . 20 LSM303DLH electrical connection 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LGA-28: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 16941 Rev 1
7/47
Block diagram and pin description
LSM303DLH
1
1.1
Block diagram and pin description
Block diagram
Figure 1. Block diagram
8/47
Doc ID 16941 Rev 1
LSM303DLH
Block diagram and pin description
1.2
Pin description
Figure 2. Pin connection
Doc ID 16941 Rev 1
9/47
Block diagram and pin description Table 2.
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
LSM303DLH
Pin description
Name Reserved GND Reserved SA0_A Reserved Vdd Reserved NC NC Reserved Reserved SET2 Reserved Reserved C1 SET1 Reserved DRDY_M SDA_M SCL_M Vdd_dig_M Vdd_IO_A Reserved SCL_A SDA_A INT1 INT2 Reserved Connect to GND 0 V supply Connect to GND Linear acceleration signal I2C less significant bit of the device address (SA0) To be connected to Vdd I2C bus Power supply Connect to Vdd Not connected Not connected Leave unconnected Leave unconnected S/R capacitor connection (C2) Leave unconnected Leave unconnected Reserved capacitor connection (C1) S/R capacitor connection (C2) Connect to GND Magnetic signal interface data ready - test point Magnetic signal interface I2C serial data (SDA) Magnetic signal interface I2C serial clock (SCL) Magnetic sensor digital power supply Linear acceleration signal interface power supply for I/O pins Connect to Vdd_IO_A Linear acceleration signal interface I2C serial clock (SCL) Linear acceleration signal interface I2C serial data (SDA) Inertial interrupt 1 Inertial interrupt 2 Connect to GND Function
10/47
Doc ID 16941 Rev 1
LSM303DLH
Module specifications
2
2.1
Module specifications
Mechanical characteristics
@ Vdd = 2.5 V, T = 25 C unless otherwise noted(a)
Table 3.
Symbol
Mechanical characteristics
Parameter Linear acceleration measurement range(2) Test conditions FS bit set to 00 Min. Typ.(1) 2.0 4.0 8.0 1.3 1.9 2.5 4.0 4.7 5.6 8.1 0.9 1.8 3.5 1 2 3.9 1055 950 795 710 635 570 430 385 375 335 320 285 230 205 LSB/ gauss 1.1 2.2 4.3 mg/digit gauss g Max. Unit
LA_FS
FS bit set to 01 FS bit set to 11 GN bits set to 001 GN bits set to 010 GN bits set to 011
M_FS
Magnetic measurement range
GN bits set to 100 GN bits set to 101 GN bits set to 110 GN bits set to 111 FS bit set to 00 12 bit representation
LA_So
Linear acceleration sensitivity
FS bit set to 01 12 bit representation FS bit set to 11 12 bit representation GN bits set to 001 (X,Y) GN bits set to 001 (Z) GN bits set to 010 (X,Y) GN bits set to 010 (Z) GN bits set to 011 (X,Y) GN bits set to 011 (Z)
M_GN
Magnetic gain setting
GN bits set to 100 (X,Y) GN bits set to 100 (Z) GN bits set to 101 (X,Y) GN bits set to 101 (Z) GN bits set to 110 (X,Y) GN bits set to 110 (Z) GN bits set to 111(2) (X,Y) GN bits set to 111(2) (Z)
a. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.5 V to 3.3 V.
Doc ID 16941 Rev 1
11/47
Module specifications Table 3.
Symbol LA_TCSo
LSM303DLH
Mechanical characteristics (continued)
Parameter Linear acceleration sensitivity change vs. temperature Linear acceleration typical zero-g level offset accuracy(3),(4) Test conditions FS bit set to 00 Min. Typ.(1) 0.01 Max. Unit %/C
LA_TyOff
FS bit set to 00
20
mg
LA_TCOff LA_An
Linear acceleration zero-g level Max delta from 25 C change vs temperature Acceleration noise density FS bit set to 00 FS bit set to 00 X axis
0.1 218 300 -300 350 1 10000 270 255 8 20 -30 +85
mg/C g/ Hz LSb LSb LSb %FS/ gauss gauss LSB LSB mgauss gauss C
LA_Vst
Linear acceleration self-test output change(5),(6),(7)
FS bit set to 00 Y axis FS bit set to 00 Z axis
M_CAS M_EF
Magnetic cross-axis sensitivity Maximum exposed field
Cross field = 0.5 gauss Happlied = 3 gauss No permitting effect on zero reading Positive bias mode, GN bits set to 100 on X, Y axis Positive bias mode, GN bits set to 100 on Z axis Vdd = 3 V Sensitivity starts to degrade. User S/R pulse to restore sensitivity
M_ST
Magnetic self test
M_R M_DF Top
Magnetic resolution Disturbing field Operating temperature range
1. Typical specifications are not guaranteed 2. Verified by wafer level test and measurement of initial offset and sensitivity 3. Typical zero-g level offset value after MSL3 preconditioning 4. Offset can be eliminated by enabling the built-in high-pass filter 5. The sign of "Self-test output change" is defined by the CTRL_REG4 STsign bit (Table 29), for all axes. 6. Self-test output changes with the power supply. "Self-test output change" is defined as OUTPUT[LSb](CTRL_REG4 ST bit=1) - OUTPUT[LSb](CTRL_REG4 ST bit=0). 1LSb=4g/4096 at 12bit representation, 2 g full-scale 7. Output data reach 99% of final value after 1/ODR+1ms when enabling self-test mode, due to device filtering
12/47
Doc ID 16941 Rev 1
LSM303DLH
Module specifications
2.2
Electrical characteristics
@ Vdd = 2.5 V, T = 25 C unless otherwise noted.
Table 4.
Symbol Vdd Vdd_IO_A Vdd_dig_M Vdd I2C Bus Idd IddPdn Top
Electrical characteristics
Parameter Supply voltage Accelerometer module power supply for I/O Magnetic module digital power supply Magnetic module I2C bus power supply Current consumption in normal mode(2) Current consumption in powerdown mode Operating temperature range T = 25C -30 Test conditions Min. 2.5 1.71 1.71 1.71 1.8 1.8 1.8 0.83 3 +85 Typ.(1) Max. 3.3 Vdd+0.1 2.0 Vdd+0.1 Unit V V V V mA A
C
1. Typical specifications are not guaranteed. 2. Magnetic sensor setting ODR = 7.5 Hz. Accelerometer sensor ODR = 50 Hz.
Doc ID 16941 Rev 1
13/47
Module specifications
LSM303DLH
2.3
2.3.1
Communication interface characteristics
Accelerometer sensor I2C - inter IC control interface
Subject to general operating conditions for Vdd and top.
Table 5.
Symbol f(SCL) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA)
I2C slave timing values
I2C standard mode (1) Parameter Min SCL clock frequency SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Bus free time between STOP and START condition 4 4.7 4 4.7 0 4.7 4.0 250 0.01 3.45 1000 300 Max 100 Min 0 1.3 s 0.6 100 0.01 20 + 0.1Cb(2) 20 + 0.1Cb(2) 0.6 0.6 s 0.6 1.3 0.9 300 ns 300 ns s Max 400 KHz I2C fast mode (1) Unit
tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(ST) tsu(SR) tsu(SP) tw(SP:SR)
1. Data based on standard I2C protocol requirement, not tested in production. 2. Cb = total capacitance of one bus line, in pF.
Figure 3.
I2C slave timing diagram (b)
b. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both port.
14/47
Doc ID 16941 Rev 1
LSM303DLH
Module specifications
2.3.2
Magnetic field sensing I2C digital interface
This magnetic sensor IC has a 7-bit serial address and supports I2C protocols with standard and fast modes (100 kHz and 400 kHz, respectively), but does not support high-speed mode (Hs). External pull-up resistors are required to support the standard and fast modes. Depending on the application, the internal pull-ups may be used to support slower data speeds than specified by I2C standards. This device does not contain 50 ns spike suppression, as required by fast mode operation in the I2C bus specification. Activities required by the master (register read and write) have priority over internal activities, such as measurement. The purpose of this priority is to prevent the master waiting and the I2C bus being engaged for longer than necessary.
Doc ID 16941 Rev 1
15/47
Absolute maximum ratings
LSM303DLH
3
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6.
Symbol Vin APOW
Absolute maximum ratings
Ratings Input voltage on any control pin (SCL, SDA) Acceleration (any axis, powered, Vdd = 2.5 V) 10,000 for 0.1 ms 3,000 for 0.5 ms Acceleration (any axis, unpowered) 10,000 for 0.1 ms Operating temperature range Storage temperature range -30 to +85 -40 to +125 Maximum value -0.3 to Vdd_IO +0.3 3,000 for 0.5 ms Unit V g g g g C C
AUNP TOP TSTG
This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part. This is an ESD sensitive device, improper handling can cause permanent damages to the part.
16/47
Doc ID 16941 Rev 1
LSM303DLH
Terminology
4
4.1
Terminology
Linear acceleration sensitivity
Linear acceleration sensitivity describes the gain of the accelerometer sensor and can be determined e.g. by applying 1 g acceleration to it. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, a 1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors.
4.2
Zero-g level
Zero-g level Offset (LA_TyOff) describes the deviation of an actual output signal from the ideal output signal if no linear acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X and Y axes, whereas the Z axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2's complement number). A deviation from the ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature; see "Linear acceleration zero-g level change vs temperature" (LA_TCOff) in Table 3. The Zero-g level tolerance (TyOff) describes the standard deviation of the range of Zero-g levels of a group of sensors.
4.3
Sleep-to-wakeup
The "sleep-to-wakeup" function, in conjunction with low-power mode, allows further reduction of system power consumption and the development of new smart applications. The LSM303DLH may be set to a low-power operating mode, characterized by lower date rate refreshing. In this way the device, even if sleeping, continues sensing acceleration and generating interrupt requests. When the sleep-to-wakeup function is activated, the LSM303DLH is able to automatically wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. With this feature the system may be efficiently switched from low-power mode to full-performance depending on user-selectable positioning and acceleration events, thus ensuring power-saving and flexibility.
Doc ID 16941 Rev 1
17/47
Functionality
LSM303DLH
5
Functionality
The LSM303DLH is a system-in-package featuring a 3D digital linear acceleration and 3D digital magnetic field detection sensor. The system includes specific sensing elements and an IC interfaces capable of measuring both the linear acceleration and magnetic field applied to it, and to provide a signal to the external world through an I2C serial interface with separated digital ouput. The sensing system is manufactured using specialized micromachining processes, while the IC interfaces are realized using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM303DLH features two data-ready signals (RDY) which indicate when a new set of measured acceleration data and magnetic data are available, thus simplifying data synchronization in the digital system that uses the device. The LSM303DLH may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. Both free-fall and wakeup can be used simultaneously on two different accelerometer interrupts.
5.1
Factory calibration
The IC interface is factory calibrated for linear acceleration sensitivity (LA_So), and linear acceleration Zero-g level (LA_TyOff). The trimming values are stored inside the device in non-volatile memory. When the device is turned on, the trimming parameters are downloaded into the registers to be used during normal operation. This allows the use of the device without further calibration.
5.2
Linear acceleration self-test operation
Self-test allows the checking of sensor functionality without moving it. The self-test function is off when the self-test bit (ST) of CTRL_REG4_A (control register 4) is programmed to `0`. When the self-test bit of CTRL_REG4_A is programmed to `1` an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full-scale through the device sensitivity. When self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
5.3
Magnetic self-test operation
To check the magnetic sensor for proper operation, a self-test feature is incorporated in which the sensor offset straps are excited to create a nominal field strength (bias field) to be measured. To implement this self-test, the least significant bits (MS1 and MS0) of configuration register A are changed from 00 to 01 (0x12 or 0b000xxx01).
18/47
Doc ID 16941 Rev 1
LSM303DLH
Functionality
By placing the mode register into single-conversion mode (0x01), two data acquisition cycles are made on each magnetic vector. The first acquisition is a set pulse followed shortly by measurement data of the external field. The second acquisition has the offset strap excited in the positive bias mode to create about a 0.6 gauss self-test field plus the external field. The first acquisition values are subtracted from the second acquisition, and the net measurement is placed into the data output registers. To leave self-test mode, change the MS1 and MS0 bits of the configuration register A back to 0x00. Also, change the mode register if single-conversion mode is not the intended next mode of operation. Table 7.
Symbol
Magnetic ST (positive bias)
GN bits setting GN bits set to 001 Z axis X,Y axis GN bits set to 010 Z axis X,Y axis GN bits set to 011 Z axis X,Y axis 375 270 LSB Z axis X,Y axis GN bits set to 101 Z axis X,Y axis GN bits set to 110 Z axis GN bits set to 111(2) X,Y axis Z axis 190 140 135 225 200 255 235 470 395 630 495 Test axis X,Y axis Min. Typ.(1) 655 Max. Unit
ST_M
GN bits set to 100
1. Typical specifications are not guaranteed
Doc ID 16941 Rev 1
19/47
Application hints
LSM303DLH
6
Application hints
Figure 4. LSM303DLH electrical connection 1 - recommended for I2C fast mode
Figure 5.
LSM303DLH electrical connection 2
20/47
Doc ID 16941 Rev 1
LSM303DLH
Application hints
6.1
External capacitors
The C1 and C2 external capacitors should have a low SR value ceramic type construction. Reservoir capacitor C1 is nominally 4.7 F in capacitance, with the set/reset capacitor C2 nominally 0.22 F in capacitance. The device core is supplied through the Vdd line. Power supply decoupling capacitors (C4=100 nF ceramic, C3=10 F Al) should be placed as near as possible to the supply pin of the device (common design practice). All the voltage and ground supplies must be present at the same time to obtain proper behavior of the IC (refer to Figure 4). The functionality of the device and the measured acceleration/magnetic field data is selectable and accessible through the I2C interface. The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user through the I2C interface.
6.2
Pull-up resistors
Pull-up resistors are placed on the two I2C bus lines.
6.3
Digital interface power supply
This digital interface dedicated to the linear acceleration signal is capable of operating with a standard power supply (Vdd) or using a dedicated power supply (Vdd_IO_A). This digital interface dedicated to the magnetic field signal requires a dedicated power supply (Vdd_dig_M). The table below shows the modes available in the various power supply conditions. Table 8.
Vdd_dig_M
Operational mode and power supply for magnetic field sensing
Vdd Mode supported All except off Description Digital I/O pins: range from GND to Vdd_I2C_bus / Vdd_dig_M. Device fully functional. Digital logic blocks are powered from Vdd_dig_M supply, including all onboard clocks.
High
High
High
Low
Digital I/O pins: range from GND to Vdd_I2C_bus / Vdd_dig_M. Power down Device measurement functionality not supported. Device I2C bus and register access supported.
6.4
Soldering information
The LGA package is compliant with the ECOPACK(R), RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave "pin 1 Indicator" unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/
Doc ID 16941 Rev 1
21/47
Application hints
LSM303DLH
6.5
High current wiring effects
High current in wiring and printed circuit traces can be the cause of errors in magnetic field measurements for compassing. Conducto-generated magnetic fields add to earth's magnetic field, creating errors in compass heading computation. Keep currents that are higher than 10 mA a few millimeters further away from the sensor IC.
22/47
Doc ID 16941 Rev 1
LSM303DLH
Digital interfaces
7
Digital interfaces
The registers embedded inside the LSM303DLH are accessible through two separate I2C serial interfaces: one for the accelerometer core and the other for the magnetometer core. The two interfaces can be connected together on the PCB. Table 9. Serial interface pin description
Pin description I2 C serial clock (SCL) for accelerometer
Pin name SCL_A SDA_A SCL_M SDA_M
I2C serial data (SDA) for accelerometer I2C serial clock (SCL) for magnetometer I2C serial data (SDA) for magnetometer
7.1
I2C serial interface
The LSM303DLH I2C is a bus slave. The I2C is employed to write the data into the registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 10.
Term Transmitter Receiver Master Slave
Serial interface pin description
Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface.
Doc ID 16941 Rev 1
23/47
Digital interfaces
LSM303DLH
7.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded inside the LSM303DLH behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7 LSb represent the actual register address while the MSB enables address auto-increment. If the MSb of the SUB field is `1', the SUB (register address) is automatically increased to allow multiple data read/write. Table 11.
Master Slave
Transfer when master is writing one byte to slave
ST SAD + W SAK SUB SAK DATA SAK SP
Table 12.
Master Slave
Transfer when master is writing multiple bytes to slave
ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP
Table 13.
Master Slave ST
Transfer when master is receiving (reading) one byte of data from slave
SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing a real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
24/47
Doc ID 16941 Rev 1
LSM303DLH
Digital interfaces
7.1.2
Linear acceleration digital interface
For linear acceleration, the default (factory) 7-bit slave address is 001100xb. The SDO/SA0 pad can be used to modify the least significant bit of the device address. If the SA0 pad is connected to voltage supply, LSb is `1' (address 0011001b) otherwise if the SA0 pad is connected to ground, LSb value is `0' (address 0011000b). This solution permits connecting and addressing two different accelerometers to the same I2C lines. The slave address is completed with a read/write bit. If the bit was `1' (read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is `0' (write) the master transmits to the slave with direction unchanged. Table 14 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 14. SAD+Read/Write patterns
SAD[6:1] 001100 001100 001100 001100 SAD[0] = SA0 0 0 1 1 R/W 1 0 1 0 SAD+R/W 00110001 (31h) 00110000 (30h) 00110011 (33h) 00110010 (32h)
Command Read Write Read Write
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of the first register to be read. In the presented communication format , MAK is Master Acknowledge and NMAK is No Master Acknowledge. Table 15.
Master Slave
Transfer when master is receiving (reading) multiple bytes of data from slave
ST SAD +W SAK SUB SAK SR SAD +R SAK DATA MAK DATA MAK DATA NMAK SP
7.1.3
Magnetic field digital interface
The system communicates via a two-wire I2C bus system as a slave device. The interface protocol is defined by the I2C bus specification. The data rate is the standard mode 100 kbps or 400 kbps rates as defined by the I2C bus specifications. The bus bit format is an 8bit data/address send and a 1-bit acknowledge bit. The format of the data bytes (payload) shall be case-sensitive ASCII characters or binary data to the magnetic sensor slave, and binary data returned. Negative binary values will be in two's complement form.
For magnetic sensor, the default (factory) 7-bit slave address is 0011110b (0x3C) for write operations, or 00111101b (0x3D) for read operations.
The Serial Clock (SCL_M) and Serial Data (SDA_M) lines have optional internal pull-up resistors, but require resistive pull-up (Rp) between the master device (usually a host microprocessor) and the LSM303DLH. Pull-up resistance values of about 10 k are recommended with a nominal 1.8 V digital supply voltage (Vdd_dig_M).
Doc ID 16941 Rev 1
25/47
Digital interfaces
LSM303DLH
The SCL_M and SDA_M lines in this bus specification can be connected to a host of devices. The bus can be a single master to multiple slaves, or it can be a multiple master configuration. All data transfers are initiated by the master device which is responsible for generating the clock signal, and the data transfers are 8 bits long. All devices are addressed by the unique 7-bit address of the I2C. After each 8-bit transfer, the master device generates a 9th clock pulse, and releases the SDA_M line. The receiving device (addressed slave) pulls the SDA_M line low to acknowledge (ACK) the successful transfer, or leaves the SDA_M high to negative acknowledge (NACK). As per the I2C specification, all transitions in the SDA_M line must occur when SCL_M is low. This requirement leads to two unique conditions on the bus associated with the SDA_M transitions when SCL_M is high. The master device pulling the SDA line low while the SCL_M line is high indicates the Start (S) condition, while the Stop (P) condition is indicated by the SDA_M line pulled high while the SCL_M line is high. The I2C protocol also allows for the Restart condition, in which the master device issues a second start condition without issuing a stop. All bus transactions begin with the master device issuing the start sequence followed by the slave address byte. The address byte contains the slave address; the upper 7 bits (bits7-1), and the least significant bit (LSb). The LSb of the address byte designates if the operation is a read (LSb=1) or a write (LSb=0). At the 9th clock pulse, the receiving slave device issues the ACK (or NACK). Following these bus events, the master sends data bytes for a write operation, or the slave clocks out data with a read operation. All bus transactions are terminated with the master issuing a stop sequence. I2C bus control can be implemented with either hardware logic or in software. Typical hardware designs release the SDA_M and SCL_M lines as appropriate to allow the slave device to manipulate these lines. In a software implementation, care must be taken to perform these tasks in code. Table 16. SAD+Read/Write patterns
SAD[6:0] 0011110 0011110 R/W 1 0 SAD+R/W 00111101 (3Dh) 00111100 (3Ch)
Command Read Write
Magnetic signal interface reading/writing
The interface uses an address pointer to indicate which register location is to be read from or written to. These pointer locations are sent from the master to this slave device and succeed the 7-bit address plus 1 bit read/write identifier. To minimize the communication between the master and magnetic digital interface of the LSM303DLH, the address pointer is updated automatically without master intervention. This automatic address pointer update has two additional features. First, when address 12 or higher is accessed the pointer updates to address 00, and secondly when address 09 is reached, the pointer rolls back to address 03. Logically, the address pointer operation functions as shown below.

if address pointer = 09, then address pointer = 03 while if address pointer >12, then address pointer = 0 while address pointer = address pointer + 1 the address pointer value itself cannot be read via the I2C bus.
Any attempt to read an invalid address location returns 0's, and any write to an invalid address location or an undefined bit within a valid address location is ignored by this device.
26/47 Doc ID 16941 Rev 1
LSM303DLH
Register mapping
8
Register mapping
The tables given below provide a listing of the 8-bit registers embedded in the device and the related addresses:
Table 17.
Register address map
Name Slave address Register address Type Hex 00 - 1F TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 rw rw rw rw rw r rw r r r r r r r 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E - 2F TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 TAB.13 rw r rw rw rw r rw rw 30 31 32 33 34 35 36 37 38 - 3F TAB.15 TAB.15 TAB.15 TAB.15 rw rw rw r 00 01 02 03 00000000 00000001 00000010 00000011 00010000 00100000 00000011 output 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Reserved 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 00000000 00000000 output output output output output output Reserved 00000111 00000000 00000000 00000000 00000000 Dummy register Binary Reserved Default Comment
Reserved (do not modify) CTRL_REG1_A CTRL_REG2_A CTRL_REG3_A CTRL_REG4_A CTRL_REG5_A HP_FILTER_RESET_A REFERENCE_A STATUS_REG_A OUT_X_L_A OUT_X_H_A OUT_Y_L_A OUT_Y_H_A OUT_Z_L_A OUT_Z_H_A Reserved (do not modify) INT1_CFG_A INT1_SOURCE_A INT1_THS_A INT1_DURATION_A INT2_CFG_A INT2_SOURCE_A INT2_THS_A INT2_DURATION_A Reserved (do not modify) CRA_REG_M CRB_REG_M MR_REG_M OUT_X_H_M
Doc ID 16941 Rev 1
27/47
Register mapping Table 17. Register address map (continued)
Name OUT_X_L_M OUT_Y_H_M OUT_Y_L_M OUT_Z_H_M OUT_Z_L_M SR_REG_Mg IRA_REG_M IRB_REG_M IRC_REG_M Slave address TAB.15 TAB.15 TAB.15 TAB.15 TAB.15 TAB.15 TAB.15 TAB.15 TAB.15 Register address Type Hex r r r r r r r r r 04 05 06 07 08 09 0A 0B 0C Binary 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 output output output output output 00000000 01001000 00110100 00110011 Default
LSM303DLH
Comment
Registers marked as Reserved must not be changed. Writing to these registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibrated values. Their content is automatically restored when the device is powered up.
28/47
Doc ID 16941 Rev 1
LSM303DLH
Registers description
9
Registers description
The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The register address, composed of 7 bits, is used to identify them and to write the data through the serial interface.
9.1
Linear acceleration register
For linear acceleration sensors, the default (factory) 7-bit slave address is 001100xb.
9.1.1
CTRL_REG1_A (20h)
Table 18.
PM2
CTRL_REG1_A register
PM1 PM0 DR1 DR0 Zen Yen Xen
Table 19.
PM2 - PM0 DR1, DR0 Zen Yen Xen
CTRL_REG1_A description
Power mode selection. Default value: 000 (000: Power-down; Others: refer to Table 20) Data rate selection. Default value: 00 (00:50 Hz; others: refer to Table 21) Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled)
PM bits allow selection between power-down and two operating active modes. The device is in power-down mode when the PD bits are set to "000" (default value after boot). Table 20 shows all the possible power mode configurations and respective output data rates. Output data in the low-power modes are computed with a low-pass filter cut-off frequency defined by DR1, DR0 bits. DR bits, in the normal-mode operation, select the data rate at which acceleration samples are produced. In low-power mode they define the output data resolution. Table 21 shows all the possible configurations for the DR1 and DR0 bits. Table 20.
PM2 0 0
Power mode and low-power output data rate configurations
PM1 0 0 PM0 0 1 Power mode selection Power-down Normal mode Output data rate [Hz] ODRLP -ODR
Doc ID 16941 Rev 1
29/47
Registers description Table 20.
PM2 0 0 1 1 1
LSM303DLH Power mode and low-power output data rate configurations (continued)
PM1 1 1 0 0 1 PM0 0 1 0 1 0 Power mode selection Low-power Low-power Low-power Low-power Low-power Output data rate [Hz] ODRLP 0.5 1 2 5 10
Table 21.
Normal-mode output data rate configurations and low-pass cut-off frequencies
DR0 0 1 0 1 Output data rate [Hz] ODR 50 100 400 1000 Low-pass filter cut-off frequency [Hz] 37 74 292 780
DR1 0 0 1 1
9.1.2
CTRL_REG2_A (21h)
Table 22.
BOOT
CTRL_REG2_A register
HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0
Table 23.
BOOT
CTRL_REG2_A description
Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) High-pass filter mode selection. Default value: 00 (00: normal mode; Others: refer to Table 24) Filtered data selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) High-pass filter enabled for interrupt 2 source. Default value: 0 (0: filter bypassed; 1: filter enabled) High-pass filter enabled for interrupt 1 source. Default value: 0 (0: filter bypassed; 1: filter enabled) High-pass filter cut-off frequency configuration. Default value: 00 (00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)
HPM1, HPM0 FDS HPen2 HPen1 HPCF1, HPCF0
The BOOT bit is used to refresh the content of internal registers stored in the Flash memory block. At device power-up, the content of the Flash memory block is transferred to the
30/47 Doc ID 16941 Rev 1
LSM303DLH
Registers description
internal registers related to trimming functions to permit good device behavior. If, for any reason, the content of the trimming registers was changed, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to `1' the content of internal Flash is copied to the corresponding internal registers and is used to calibrate the device. These values are factory-trimmed and are different for every accelerometer. They permit good device behavior and normally do not have to be modified. At the end of the boot process, the BOOT bit is again set to `0'. Table 24.
HPM1 0 0 1
High-pass filter mode configuration
HPM0 0 1 0 High-pass filter mode Normal mode (reset reading HP_RESET_FILTER) Reference signal for filtering Normal mode (reset reading HP_RESET_FILTER)
HPCF[1:0]. These bits are used to configure the high-pass filter cut-off frequency ft,which is given by:
fs 1f t = ln 1 - ----------- ----- 2 HPc
The equation can be simplified to the following approximated equation:
fs f t = --------------------6 HPc
Table 25.
HPcoeff2,1 00 01 10 11
High-pass filter cut-off frequency configuration
ft [Hz] Data rate = 50 Hz 1 0.5 0.25 0.125 ft [Hz] Data rate = 100 Hz 2 1 0.5 0.25 ft [Hz] ft [Hz] Data rate = 400 Hz Data rate = 1000 Hz 8 4 2 1 20 10 5 2.5
9.1.3
CTRL_REG3_A (22h)
Table 26.
IHL
CTRL_REG3_A register
PP_OD LIR2 I2_CFG1 I2_CFG0 LIR1 I1_CFG1 I1_CFG0
Doc ID 16941 Rev 1
31/47
Registers description
LSM303DLH
Table 27.
IHL PP_OD
CTRL_REG3_A description
Interrupt active high, low. Default value: 0 (0: active high; 1:active low) Push-pull/open drain selection on interrupt pad. Default value 0. (0: push-pull; 1: open drain) Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by reading INT2_SRC itself. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Data signal on INT 2 pad control bits. Default value: 00. (see table below) Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC register. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Data signal on INT 1 pad control bits. Default value: 00. (see table below)
LIR2 I2_CFG1, I2_CFG0 LIR1 I1_CFG1, I1_CFG0
Table 28.
Data signal on INT 1 and INT 2 pad
I1(2)_CFG0 0 1 0 1 INT 1(2) Pad Interrupt 1 (2) source Interrupt 1 source OR interrupt 2 source Data ready Boot running
I1(2)_CFG1 0 0 1 1
9.1.4
CTRL_REG4_A (23h)
Table 29.
BDU
CTRL_REG4_A register
BLE FS1 FS0 STsign 0 ST ---
Table 30.
BDU BLE FS1, FS0 STsign ST
CTRL_REG4_A description
Block data update. Default value: 0 (0: continuos update; 1: output registers not updated between MSB and LSB reading) Big/little endian data selection. Default value 0. (0: data LSB @ lower address; 1: data MSB @ lower address) Full-scale selection. Default value: 00. (00: 2 g; 01: 4 g; 11: 8 g) Self-test sign. Default value: 00. (0: self-test plus; 1 self-test minus) Self-test enable. Default value: 0. (0: self-test disabled; 1: self-test enabled)
32/47
Doc ID 16941 Rev 1
LSM303DLH
Registers description
The BDU bit is used to inhibit output register updates between the reading of the upper and lower register parts. In default mode (BDU = `0'), the lower and upper register parts are updated continuously. If it is not certain to read faster than output data rate, it is recommended to set BDU bit to `1'. In this way, after the reading of the lower (upper) register part, the content of that output register is not updated until the upper (lower) part is read also. This feature avoids reading LSB and MSB related to different samples.
9.1.5
CTRL_REG5_A (24h)
Table 31.
0
CTRL_REG5_A register
0 0 0 0 0 TurnOn1 TurnOn0
Table 32.
TurnOn1, TurnOn0
CTRL_REG5_A description
Turn-on mode selection for sleep-to-wake function. Default value: 00.
TurnOn bits are used for turning on the sleep-to-wake function. Table 33.
TurnOn1 0 1
Sleep-to-wake configuration
TurnOn0 0 1 Sleep-to-wake status Sleep-to-wake function is disabled Turned on: The device is in low-power mode (ODR is defined in CTRL_REG1_A)
By setting the TurnOn [1:0] bits to 11, the "sleep-to-wake" function is enabled. When an interrupt event occurs, the device goes into normal mode, increasing the ODR to the value defined in CTRL_REG1_A. Although the device is in normal mode, CTRL_REG1_A content is not automatically changed to "normal mode" configuration.
9.1.6
HP_FILTER_RESET_A (25h)
Dummy register. Reading at this address instantaneously zeroes the content of the internal high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to 0 g. This makes it possible to surmount the settling time of the high-pass filter.
9.1.7
REFERENCE_A (26h)
Table 34.
Ref7
REFERENCE_A register
Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0
Table 35.
Ref7 - Ref0
REFERENCE_A description
Reference value for high-pass filter. Default value: 00h.
Doc ID 16941 Rev 1
33/47
Registers description
LSM303DLH
This register sets the acceleration value taken as a reference for the high-pass filter output. When the filter is turned on (at least one FDS, HPen2, or HPen1 bit is equal to `1') and HPM bits are set to "01", filter out is generated taking this value as a reference.
9.1.8
STATUS_REG_A(27h)
Table 36.
ZYXOR
STATUS_REG_A register
ZOR YOR XOR ZYXDA ZDA YDA XDA
Table 37.
ZYXOR
STATUS_REG_A description
X, Y and Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data has overwritten the previous one before it was read) Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous one) Y axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous one) X axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous one) X, Y and Z axis new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Z axis new data available. Default value: 0 (0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available) Y axis new data available. Default value: 0 (0: new data for the Y-axis is not yet available; 1: new data for the Y-axis is available) X axis new data available. Default value: 0 (0: new data for the X-axis is not yet available; 1: new data for the X-axis is available)
ZOR
YOR
XOR ZYXDA ZDA
YDA
XDA
9.1.9
OUT_X_L_A (28h), OUT_X_H_A (29h)
X-axis acceleration data. The value is expressed as two's complement.
9.1.10
OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh)
Y-axis acceleration data. The value is expressed as two's complement.
9.1.11
OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh)
Z-axis acceleration data. The value is expressed as two's complement.
34/47
Doc ID 16941 Rev 1
LSM303DLH
Registers description
9.1.12
INT1_CFG_A (30h)
Table 38.
AOI
INT1_CFG_A register
6D ZHIE ZLIE YHIE YLIE XHIE XLIE
Table 39.
AOI 6D
INT1_CFG_A description
AND/OR combination of interrupt events. Default value: 0. (See Table 40) 6 direction detection function enable. Default value: 0. (See Table 40) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Configuration register for Interrupt 1 source. Table 40.
AOI 0 0 1 1
Interrupt 1 source configurations
6D 0 1 0 1 Interrupt mode OR combination of interrupt events 6 direction movement recognition AND combination of interrupt events 6 direction position recognition
Doc ID 16941 Rev 1
35/47
Registers description
LSM303DLH
9.1.13
INT1_SRC_A (31h)
Table 41.
0
INT1_SRC register
IA ZH ZL YH YL XH XL
Table 42.
IA ZH ZL YH YL XH XL
INT1_SRC_A description
Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) X high. Default value: 0 (0: no interrupt, 1: X high event has occurred) X low. Default value: 0 (0: no interrupt, 1: X low event has occurred)
Interrupt 1 source register. Read-only register. Reading at this address clears INT1_SRC_A IA bit (and the interrupt signal on INT 1 pin) and allows the refreshing of data in the INT1_SRC_A register if the latched option was chosen.
9.1.14
INT1_THS_A (32h)
Table 43.
0
INT1_THS register
THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 44.
INT1_THS description
Interrupt 1 threshold. Default value: 000 0000
THS6 - THS0
9.1.15
INT1_DURATION_A (33h)
Table 45.
0
INT1_DURATION_A register
D6 D5 D4 D3 D2 D1 D0
Table 46.
D6 - D0 36/47
INT2_DURATION_A description
Duration value. Default value: 000 0000 Doc ID 16941 Rev 1
LSM303DLH
Registers description
The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen.
9.1.16
INT2_CFG_A (34h)
Table 47.
AOI
INT2_CFG_A register
6D ZHIE ZLIE YHIE YLIE XHIE XLIE
Table 48.
AOI 6D
INT2_CFG_A description
AND/OR combination of interrupt events. Default value: 0. (See table below) 6 direction detection function enable. Default value: 0. (See table below) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Configuration register for Interrupt 2 source. Table 49.
AOI 0 0 1 1
Interrupt mode configuration
6D 0 1 0 1 Interrupt mode OR combination of interrupt events 6 direction movement recognition AND combination of interrupt events 6 direction position recognition
Doc ID 16941 Rev 1
37/47
Registers description
LSM303DLH
9.1.17
INT2_SRC_A (35h)
Table 50.
0
INT2_SRC_A register
IA ZH ZL YH YL XH XL
Table 51.
IA ZH ZL YH YL XH XL
INT2_SRC_A description
Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) X high. Default value: 0 (0: no interrupt, 1: X high event has occurred) X Low. Default value: 0 (0: no interrupt, 1: X low event has occurred)
Interrupt 2 source register. Read-only register. Reading at this address clears INT2_SRC_A IA bit (and the interrupt signal on INT 2 pin) and allows the refreshing of data in the INT2_SRC_A register if the latched option was chosen.
9.1.18
INT2_THS_A (36h)
Table 52.
0
INT2_THS register
THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 53.
INT2_THS description
Interrupt 1 threshold. Default value: 000 0000
THS6 - THS0
9.1.19
INT2_DURATION_A (37h)
Table 54.
0
INT2_DURATION_A register
D6 D5 D4 D3 D2 D1 D0
Table 55.
D6 - D0
INT2_DURATION_A description
Duration value. Default value: 000 0000
38/47
Doc ID 16941 Rev 1
LSM303DLH
Registers description
The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen.
9.2
Magnetic field sensing register description
The magnetometer core contains a set of registers which are used to control its behavior and to retrieve magnetic field data. The register's address, composed of 8 bits, is used to identify them and to read/write the data through the serial interface. For magnetic field sensing interface, the default (factory) 7-bit slave address is 00111100b (0x3C) for write operations, or 00111101b (0x3D) for read operations.
9.2.1
CRA_REG_M (00h)
The configuration register A is used to configure the device for setting the data output rate and measurement configuration. CRA0 through CRA7 indicate bit locations, with CRA denoting the bits that are in the configuration register. CRA7 denotes the first bit of the data stream. The number in parentheses indicates the default value of that bit. Table 56.
0
CRA_REG_M register
0 0 DO2 DO1 DO0 MS1 MS0
Table 57.
CRA_REG_M description
Data output rate bits. These bits set the rate at which data is written to all three data output registers Measurement configuration bits. These bits define the measurement flow of the device, specifically whether or not to incorporate an applied bias to the sensor into the measurement
CRA7 to CRA5 These bits must be cleared for correct operation. DO2 to DO0
MS1 to MS0
Table 58.
DO2 0 0 0 0 1 1 1 1
CRA_REG M description
DO1 0 0 1 1 0 0 1 1 DO0 0 1 0 1 0 1 0 1 Minimum data output rate (Hz) 0.75 1.5 3.0 7.5 15 30 75 Not used
Doc ID 16941 Rev 1
39/47
Registers description
LSM303DLH
Table 59.
MS1 0 0 1 1
CRA_REG_M description
MS0 0 1 0 1 Magnetic sensor operating mode Normal measurement configuration (default). In normal measurement configuration the device follows normal measurement flow. Positive bias configuration. Negative bias configuration. This configuration is not used
9.2.2
CRB_REG_M (01h)
The configuration register B for setting the device gain. CRB0 through CRB7 indicate bit locations, with CRB denoting the bits that are in the configuration register. CRB7 denotes the first bit of the data stream. The number in parentheses indicates the default value of that bit. Table 60.
GN2
CRA_REG register
GN1 GN0 0 0 0 0 0
Table 61.
CRA_REG description
Gain configuration bits. These bits configure the gain for the device. The gain configuration is common for all channels
CRB7 to CRB5
CRB7 to CRB5 This bit must be cleared for correct operation
Table 62.
GN2
Gain setting
GN0 Sensor input field range [Gauss] 1.3 1.9 2.5 4.0 4.7 5.6 8.1 Gain X/Y and Z [LSB/Gauss] 1055 795 635 430 375 320 230 Gain Z [LSB/Gauss] 950 710 570 385 335 285 205 0xF800-0x07FF (-2048-2047) Output range
GN1
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
9.2.3
MR_REG_M (02h)
The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to select the operating mode of the device. MR0 through MR7 indicate bit locations, with MR denoting the bits that are in the mode register. MR7 denotes
40/47
Doc ID 16941 Rev 1
LSM303DLH
Registers description
the first bit of the data stream. The number in parentheses indicates the default value of that bit. Table 63.
0
MR_REG
0 0 0 0 0 MD1 MD0
Table 64.
MR7 to MR2 MR1 to MR0
MR_REG description
These bits must be cleared for correct operation Mode select bits. These bits select the operation mode of this device.
Table 65.
MD1
Magnetic sensor operating mode
MD0 Mode Continuous-conversion mode: the device continuously performs conversions and places the result in the data register. RDY goes high when new data is placed in all three registers. After a power-on or a write to the mode or configuration register, the first measurement set is available from all three data output registers after a period of 2/fDO, and subsequent measurements are available at a frequency of fDO, where fDO is the frequency of data output. Single-conversion mode: the device performs a single measurement, sets RDY high and returns to sleep mode. Mode register returns to sleep mode bit values. The measurement remains in the data output register and RDY remains high until the data output register is read or another conversion is performed. -Sleep mode. Device is placed in sleep mode
0
0
0
1
1 1
0 1
9.2.4
OUT_X_M (03-04h)
The data output X registers are two 8-bit registers, data output register H and data output register L. These registers store the measurement result from channel X. Data output X register H contains the MSB from the measurement result, and data output X register L contains the LSB from the measurement result. The value stored in these two registers is a 16-bit value in 2's complement form, whose range is 0xF800 to 0x07FF. DXRH0 through DXRH7 and DXRL0 through DXRL7 indicate bit locations, with DXRH and DXRL denoting the bits that are in the data output X registers. DXRH7 and DXRL7 denote the first bit of the data stream. In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias measurement, this data register will contain the value -4096 in 2's complement form. This register value clears after the next valid measurement is made. Table 66.
DXRH7
OUTXH_M register
DXRH6 DXRH5 DXRH4 DXRH3 DXRH2 DXRH1 DXRH0
The content of this register is the MSB magnetic field data for X-axis.
Doc ID 16941 Rev 1 41/47
Registers description
LSM303DLH
Table 67.
DXRL7
OUTXL_M register
DXRL6 DXRL5 DXRL4 DXRL3 DXRL2 DXRL1 DXRL0
The content of this register is the LSB magnetic field data for X-axis.
9.2.5
OUT_Y_M (05-06h)
The data output Y registers are two 8-bit registers, data output register H and data output register L. These registers store the measurement result from channel Y. Data output Y register H contains the MSB from the measurement result, and data output Y register L contains the LSB from the measurement result. Table 68.
DYRH7
OUT_YH_M register
DYRH6 DYRH5 DYRH4 DYRH3 DYRH2 DYRH1 DYRH0
The content of this register is the MSB magnetic field data for Y-axis. Table 69.
DYRL7
OUT_YL_M register
DYRL6 DYRL5 DYRL4 DYRL3 DYRL2 DYRL1 DYRL0
The content of this register is the LSB magnetic field data for Y-axis.
9.2.6
OUT_Z_M (07-08h)
The data output Z registers are two 8-bit registers, data output register H and data output register L. These registers store the measurement result from channel Z. Data output Z register H contains the MSB from the measurement result, and data output Z register L contains the LSB from the measurement result. Table 70.
DZRH7
OUTZH_M register
DZRH6 DZRH5 DZRH4 DZRH3 DZRH2 DZRH1 DZRH0
The content of this register is the MSB magnetic field data for Z-axis. Table 71.
DZRL7
OUTZL_M register
DZRL6 DZRL5 DZRL4 DZRL3 DZRL2 DZRL1 DZRL0
The content of this register is the LSB magnetic field data for Z-axis.
9.2.7
SR_REG_M (09h)
When one or more of the output registers are read, new data cannot be placed in any of the output data registers until all six data output registers are read. This requirement also
42/47
Doc ID 16941 Rev 1
LSM303DLH
Registers description
impacts DRDY and RDY, which cannot be cleared until new data is placed in all the output registers.
Status register
The status register (SR) is an 8-bit read-only register. This register is used to indicate device status. SR0 through SR7 indicate bit locations, with SR denoting the bits that are in the status register. SR7 denotes the first bit of the data stream. Table 72.
0
SR register
0 0 0 0 REN LOC RDY
Table 73.
MD1 SR7 to SR3 SR2
Status register bit designations
MD0 0 REN Mode These bits must be cleared for correct operation Regulator enabled bit. This bit is set when the internal voltage regulator is enabled. This bit is cleared when the internal regulator is disabled. Data output register lock. This bit is set when some, but not all, of the six data output registers have been read. When this bit is set, the six data output registers are locked and any new data is not placed in these registers until one of four conditions are met: one, all six have been read or the mode changed, two, a POR is issued, three, the mode is changed, or four, the measurement is changed. Ready bit. Set when data is written to all six data registers. Cleared when the device initiates a write to the data output registers, when in off mode, and after one or more of the data output registers are written to. When RDY bit is clear, it shall remain cleared for a minimum of 5 s. The DRDY pin can be used as an alternative to the status register for monitoring the device for conversion data.
SR1
LOCK
SR0
RDY
9.2.8
IR_REG_M (0Ah/0Bh/0Ch)
The identification registers (IR) are used to identify the device. IR0 through IR7 indicate bit locations, with IRA/IRB/IRC denoting the bits that are in the identification registers A, B & C. IRA7/IRB7/IRC7 denotes the first bit of the data stream. The identification value for this device is stored in this register. This is a read-only register. Register values. ASCII value H Table 74.
0
IRA_REG_M
1 0 0 1 0 0 0
Table 75.
0
IRB_REG_M
0 1 1 0 1 0 0
Doc ID 16941 Rev 1
43/47
Registers description
LSM303DLH
Table 76.
0
IRC_REG_M
0 1 1 0 0 1 1
44/47
Doc ID 16941 Rev 1
LSM303DLH
Package information
10
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 6. LGA-28: mechanical data and package dimensions
Dimensions Ref. Min.
A1 A2 A3 D1 E1 L1 L2 N1 M T1 T2 d k h 0.040 0.260 0.360 4.850 4.850 0.785 0.200 5.000 5.000 1.650 3.300 0.550 0.100 0.300 0.400 0.200 0.050 0.100 0.160 0.340 0.440 5.150 5.150
mm Typ. Max.
1
Outline and mechanical data
LGA-28 (5x5x1) Land Grid Array Packages
8192208_B
Doc ID 16941 Rev 1
45/47
Revision history
LSM303DLH
11
Revision history
Table 77.
Date 18-Dec-2009
Document revision history
Revision 1 First issue. Changes
46/47
Doc ID 16941 Rev 1
LSM303DLH
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
Doc ID 16941 Rev 1
47/47

▲Up To Search▲

Price & Availability of LSM303DLH

	To Download LSM303DLH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .